The traditional phase change memory is operating in the unipolar mode, which means that the reset current and the set current are in the same direction. The memory state is defined by the phase of the phase change material, i.e. the amorphous phase for the high-R (high-resistance) state and the crystalline phase for the low-resistor (low-resistance) state. Cells operated in the unipolar mode can have a small array size, good data retention under a low temperature range (under 85° C.), very good cycling endurance and a high operation speed.
Please refer to FIG. 1(a), which shows a conventional unipolar addressing circuit for a memory cell. The memory cell 101 includes a first electrode 1011, a second electrode 1012 and a memory material 1013 located between the first electrode 1011 and the second electrode 1012. The unipolar addressing circuit 102 includes a transistor 103, a bit line 104, a word line 105 and a source line 107.
Please refer to FIG. 1(b), which shows the waveform of the gate voltage in the unipolar operation mode of FIG. 1(a). The transverse axle represents the time, and the unit thereof is nanosecond; the vertical axle represents the voltage, and the unit thereof is voltage. In FIG. 1(b), the waveform WF1 represents the waveform of the voltage Vg1 applied to the gate of the transistor 103, and the voltage Vg1 is the voltage VWL1 applied to the word line 105. In FIG. 1(a), a first bias operation of the addressing circuit 102 is provided to the memory cell 101. The first bias operation enables the memory cell 101 to be programmed to a high-R state. The first bias operation includes applying a voltage VBL1 of 4 V to the bit line 104, applying the voltage VWL1 to the word line 105, applying a voltage Vsub of 0 V to the substrate B of the transistor 103, and applying a voltage VSL1 of 0 V to the source line 107.
In FIG. 1(b), the rising time, duration time and falling time of the waveform WF1 are 19 ns, 70 ns and 2 ns respectively. The voltage VWL1 rises from 0 V to 2.4 V in 19 ns and is kept at 2.4 V for 70 ns; at this time, the current passing through the memory cell 101 is the relatively higher current I1 which is 600 μA, as shown in FIG. 1(a). Then, the voltage VWL1 falls from 2.4 V to 0 V in 2 ns. The waveform WF1 forms the process of high current and rapid falling, which causes an amorphous phase change for the memory material 1013. The amorphous phase change will result in a high-R state of the memory material 1013.
Please refer to FIG. 1(c), which shows another conventional unipolar addressing circuit for a memory cell. The unipolar addressing circuit 112 of FIG. 1(c) differs from the unipolar addressing circuit 102 of FIG. 1(a) in that the voltage applied to the word line 105 is VWL2. Please refer to FIG. 1(d), which shows the waveform of the gate voltage in the unipolar operation mode of FIG. 1(c). The transverse axle represents the time, and the unit thereof is nanosecond; the vertical axle represents the voltage, and the unit thereof is voltage. In FIG. 1(d), the waveform WF2 represents the waveform of the voltage Vg2 applied to the gate of the transistor 103, and the voltage Vg2 is the voltage VWL2 applied to the word line 105. In FIG. 1(c), a second bias operation of the unipolar addressing circuit 102 is provided to the memory cell 101. The second bias operation enables the memory cell 101 to be erased to a low-R state. The second bias operation includes applying a voltage VBL1 of 4 V to the bit line 104, applying the voltage VWL2 to the word line 105, applying a voltage Vsub of 0 V to the substrate B of the transistor 103, and applying a voltage VSL1 of 0 V to the source line 107.
In FIG. 1(d), the rising time, duration time and falling time of the waveform WF2 are 100 ns, 400 ns and 2000 ns respectively. The voltage VWL2 rises from 0 V to 1.2 V in 100 ns and is kept at 1.2 V for 400 ns; at this time, the current passing through the memory cell 101 is the relatively lower current I2 which is 350 μA, as shown in FIG. 1(c). Then, the voltage VWL2 falls relatively slowly from 1.2 V to 0 V in 2000 ns. The waveform WF2 forms the process of low current and slow falling, which causes a crystalline phase change for the memory material 1013. The crystalline phase change will result in a low-R state of the memory material 1013.
Although the memory cell array operated in the unipolar mode and formed by the memory cell 101 has the above-mentioned advantages, when it is exposed to high temperature, the amorphous state of the memory cell 101 can be annealed, which causes the material to transform from an amorphous phase into a crystalline phase of the low-R state. That is, the data stored in the memory cell 101 are erased due to high temperature, which is the disadvantage of the memory cell 101 operated in the unipolar mode.
Another operation mode is called the bipolar operation mode, which enables the memory cell to be immune to temperature. Please refer to FIG. 2(a), which shows a conventional bipolar addressing circuit for a memory cell. The memory cell 201 includes a third electrode 2011, a fourth electrode 2012, and a memory material 2013 located between the third electrode 2011 and the fourth electrode 2012. The bipolar addressing circuit 202 includes a transistor 203, a bit line 204, a word line 205 and a source line 207.
Please refer to FIG. 2(b), which shows the waveform of the gate voltage in the bipolar operation mode of FIG. 2(a). The transverse axle represents the time, and the unit thereof is nanosecond; the vertical axle represents the voltage, and the unit thereof is voltage. In FIG. 2(b), the waveform WF3 represents the waveform of the voltage Vg3 applied to the gate of the transistor 203, and the voltage Vg3 is the voltage VWL3 applied to the word line 205. In FIG. 2(a), a third bias operation of the bipolar addressing circuit 202 is provided to the memory cell 201. The third bias operation enables the memory cell 201 to be programmed to a high-R state. The third bias operation includes applying a voltage VBL2 of 0 V to the bit line 204, applying the voltage VWL3 to the word line 205, applying a voltage Vsub of 0 V to the substrate B of the transistor 203, and applying a voltage VSL2 of 4 V to the source line 207.
In FIG. 2(b), the rising time, duration time and falling time of the waveform WF3 are 100 ns, 400 ns and 2000 ns respectively. The voltage VWL3 rises from 0 V to 3.8 V in 100 ns and is kept at 3.8 V for 400 ns; at this time, the current I3 passing through the memory cell 201 is 400 μA, as shown in FIG. 2(a). Then, the voltage VWL3 falls from 3.8 V to 0 V in 2000 ns. In the third bias operation, the electrically insulating layer (not shown) in the memory material 2013 is separated therefrom, which results in a high-R state for the memory material 2013. The insulating layer comprises one or more voids. The memory material 2013 comprises a bulk material and a doping material (not shown). The bipolar operation mode comprises a first and second bias arrangements. The first bias arrangement induces segregation of the doping material from the bulk material to form the insulating layer of the doping material. The second bias arrangement induces re-absorption of the doping material into the bulk material. The bulk material comprises a chalcogenide material, and the doping material comprises a dielectric material.
Please refer to FIG. 2(c), which shows another conventional bipolar addressing circuit for a memory cell. The bipolar addressing circuit 212 of FIG. 2(c) differs from the bipolar addressing circuit 202 of FIG. 2(a) in that the voltage applied to the word line 205 is VWL3, the voltage VBL4 applied to the bit line 204 is 4 V, and the voltage VSL3 applied to the source line 207 is 0V.
Please refer to FIG. 2(d), which shows the waveform of the gate voltage in the bipolar operation mode of FIG. 2(c). The transverse axle represents the time, and the unit thereof is nanosecond; the vertical axle represents the voltage, and the unit thereof is voltage. In FIG. 2(d), the waveform WF4 represents the waveform of the voltage Vg4 applied to the gate of the transistor 203, and the voltage Vg4 is the voltage VWL4 applied to the word line 205. In FIG. 2(d), a fourth bias operation of the bipolar addressing circuit 212 is provided to the memory cell 201. The fourth bias operation enables the memory cell 201 to be erased to a low-R state. The fourth bias operation includes applying a voltage VBL3 of 4 V to the bit line 204, applying the voltage VWL4 to the word line 205, applying a voltage Vsub of 0 V to the substrate B of the transistor 203, and applying a voltage VSL3 of 0 V to the source line 207.
In FIG. 2(d), the rising time, duration time and falling time of the waveform WF4 are 100 ns, 400 ns and 2000 ns respectively. The voltage VWL4 rises from 0 V to 1.2 V in 100 ns and is kept at 1.2 V for 400 ns; at this time, the current I4 passing through the memory cell 201 is 350 μA, as shown in FIG. 2(c). Then, the voltage VWL4 falls from 1.2 V to 0 V in 2000 ns. Since the fourth bias operation uses an opposite voltage polarity to that of the third bias operation, at least a part of the electrically insulating layer (not shown) in the memory material 2013 is merged thereinto, which results in a low-R state for the memory material 2013.
The memory cell 201 in the bipolar operation mode is much more immune to high temperature. That is, the data stored in such mode can pass the soldering process or is more reliable for critical applications. However, the memory array operated in the bipolar mode and formed by the memory cell 201 has a larger size. Besides, the bias circuit in such mode is more complicated, and has a slower operation speed. Therefore, it is important to manufacture a memory cell array having the advantages of the unipolar operation and the bipolar operation at the same time.
In order to overcome the drawbacks in the prior art, a memory device and the method of operating the same is provided. The particular design in the present invention not only solves the problems described above, but also is easy to be implemented. Thus, the present invention has the utility for the industry.